Low Power Transition Delay Fault Pattern Generation

This paper describes a low-power test generation procedure, which targets the switching activity during the fast functional clock cycles of broadside tests. The procedure is based on merging of test cubes that it extracts from functional broadside tests. The use of test cube merging supports test compaction and it can be used for accommodating the constraints of test data compression. The use of functional broadside tests provides a target for the switching activity of low-power tests, which does not exceed the switching activity that is possible during functional operation, or that the circuit is designed for. The use of test cubes that are extracted from functional broadside tests is a unique feature of this procedure. It ensures that the low-power tests would create functional operation conditions in subcircuits that are defined by the test cubes. Experimental results show that the procedure detects all or almost all the transition faults that are detectable by arbitrary (functional and nonfunctional) broadside tests in